This invention relates to an oversampling delta-sigma modulator for audio applications on high frequency A/D or D/A converters. When the modulator is applied to A/D converters, the digital code of output is sent to digital filters to be converted to PCM signals. When the modulator is applied to D/A converters, the digital output code is sent to a switched-capacitor circuit to be converted to an analog waveform with high precision.
The prior structure of delta-sigma modulators can be seen, for example, in J. C. Candy, "A use of double integration in sigma-delta modulation", IEEE, Trans. Comm. COM-33, pp 249-258, Mar., 1985. Also see, for example, Uchimura et. al., "An oversampling converter", U.S. Pat. No. 4,704,600.
FIG. 1 is the prior art of a second order delta-sigma modulator in the z-domain. The bandwidth of the input signal is much lower than the sampling rate. The adder 12 adds the input signal and the negative feedback of output signal Y together, and sends the results to an integrator 13. The integrated output is then sent to an adder 14 to be combined with the negative feedback of output Y. The derived value of the adder 14 is then sent to a delay integrator 15. Finally, the comparator compares the output of the delay integrator 15 and threshold voltages to produce the next output digital code. The comparator has one or two threshold voltages. If the integrated value is larger than the threshold voltage, then the output digital code Y will be 1, else the output code will be -1.
The transfer function of the overall system can be seen from z-domain. If the comparator is thought to be an adder with extra Q(z) input, where Q(z) is the z-transform of the difference between comparator input and output, then EQU Y(z)=X(z)z.sup.-1 +(1-z.sup.-1).sup.2 Q(z) (1)
Equation (1) shows that the output code Y contains the low frequency signal X and high frequency quantization noise after differentiating. Hence, the signal to noise ratio will be decreased in the low frequency signal band. The high resolution signal is derived by using a low pass filter to filter the high frequency quantization noise. This structure must finish the integration of the integrators 13 and 15, and the comparison of the comparator 16. In the two phase clock, phase A must finish integration and comparison, while phase B must finish integration. Hence, the clock rate is limited by phase A. So, the structure is not suitable for high frequency operation. From another point of view, the bandwidth of the operational amplifier and the speed of the comparator will be double.
When the structure of FIG. 1 is cascaded with a first order converter, the quantization noise of the first order converter can be the input of FIG. 1. By combining the outputs of the first order converter and FIG. 1, the overall system with third order differentiated noise is stable when the input operates below -2 dBr. But the settling characteristic is degraded due to the critical path of FIG. 1.
FIG. 2 is another oversampling converter for high resolution applications. BL1, BL2, and BL3 are stable first order oversampling converters. The adder 207 receives the quantization noise of BL1 and sends it to the input of BL2. Also, the adder 208 receives the quantization noise of BL2 and sends it to the input of BL3. The output codes of BL1, BL2, and BL3 are then digitally calculated to derive the characteristic of the third order differentiated noise plus signal, so the equivalent quantization noise is further decreased without stability problems. The cost of the circuit is the 3-stage cascade of the first order converters and larger digital circuits.
It is an object of the present invention to provide an oversampling converter with simpler structure than that of the conventional oversampling converter.
It is another object of the present invention to provide an oversampling converter which can operate on high frequency.
It is still another object of the present invention to provide an oversampling converter with lower quantization noise.
It is still another object of the present invention to provide an oversampling converter with fewer output levels.
In order to achieve the above objects, the present invention provides one structure by adapting an analog differentiator to modify the two stage cascade of first order converters to a third order delta-sigma converter. The analog differentiator can be implemented with an SC differentiator or delay element.
In accordance with a preferred embodiment of the invention, an input signal having a bandwidth much lower than the sampling frequency is sent to a first order converter having an integrator and comparator. The output of the integrator in this stage enters the second order converter configured by a differentiator, integrator, and comparator. The output of the delay integrator is sent to the differentiator to produce one delay term after differentiating. Also, the output codes of the first input stage and that of the second stage plus its derivative are digitally calculated and adapt negative feedback to control the voltage reference by using switched-capacitor method. The controlled values of the voltage reference are then sent back to the input of the second stage. Hence, the critical path among integrator, comparator and differentiator will be canceled and the operation speed can be doubled.
Due to the two stage cascade of the invention, the output code is derived from the result of the first stage output and the derivative of the second stage output. Hence, the real output has only four levels in comparison with seven levels of a three stage cascade. So, the digital or analog filter will be simpler.
When the structure is implemented by digital methods, the output of the differentiator can be subtracted by the comparator input of the first stage. The resultant circuit has a higher signal to noise ratio due to the higher order noise shaping effect.